SPACER ENGINEERED FINFET ARHITECTURES: HIGH-PERFORMANCE DIGITAL CIRCUIT APPLICATIONS

This book focuses on the spacer engineering aspects of novel MOS-based device–circuit co-design in sub-20nm technology nodes, its process complexity, variability, and reliability issues. It comprehensively explores the FinFET/tri-gate architectures with their circuit/SRAM suitability and tolerance to random statistical variations.